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Astera Labs logo

Technical Lead Digital Design Engineer

Astera Labs · San Jose, CA · Posted 3 days ago

$160k–$200kmgr
5+ yrs expSystemVerilogPythonRTL designSynopsysCadencePCIeEthernetDDR

Overview Join our team as Technical Lead Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.

Key Responsibilities

  • Own the RTL implementation of complex digital designs from micro-architecture through sign-off.
  • Collaborate with verification teams to review test plans and debug issues.
  • Support efforts to achieve timing closure and implement Design-for-Test (DFT) features.
  • Scripting and automation for ASIC methodology improvement.
  • Accountable for quality and overall design success with the support of senior engineers.

Required Qualifications Education & Experience:

  • Bachelor’s degree in electrical engineering or equivalent
  • 5+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets

Digital Design Expertise:

  • Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence.
  • Track record of delivering high-quality digital designs from definition to production.
  • Experience in high-speed design in advanced technology nodes.
  • Understanding of functional and formal verification at block and chip level.
  • Understanding of clocking, CDC and RDC and static-timing analysis

Protocols & Integration:

  • Proficient with high-speed protocols such as PCIe, Ethernet, DDR, or similar
  • Experience with IP development and integration

Tools & Methodologies:

  • Expertise in design methodology , CAD automation or design infrastructure.
  • Proven SystemVerilog and Python expertise in a production environment
  • Familiarity with Synopsys and/or Cadence digital design flows
  • Basic understanding of UVM-based verification methodologies

Professional Attributes:

…

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